Synopsys jobs
Subscribe to RSS Feed| Posted | Job Title | Company | Location |
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Featured Job Postings from the Web
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| Feb 07 | Intern Component Design Engg | Intel | Folsom, CA |
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ility to work independently - Experience with Application Specific Integrated Circuit (ASIC) design tools such as Modelsim * logic simulator, Synopsys * Design Compiler, Synopsys... more |
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| Feb 07 | Sr. Design Automation Engineer | Intel | Santa Clara, CA |
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routing and clocking flows - Experience with Synopsys Design Compiler, DFT Compiler and ... with cross-tool correlation between Synopsys design tools (e.g., Design Compiler,... more |
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| Feb 07 | Graphics Power Intern | Intel | Folsom, CA |
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. - Ability to work independently. - Experience with Application Specific Integrated Circuit (ASIC) design tools such as VCS logic simulator, Synopsys * Design Compiler, Synopsys... more |
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| Feb 07 | Senior Graphics Hardware Eng | Intel | Folsom, CA |
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design tools such as VCS logic simulator, Synopsys * backend tools - System Verilog/Verilog languages, OVM test methodology - Software or scripting skills (Perl, Python, Ruby, C/C... more |
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| Feb 07 | Design Automation Engineer | Intel | Phoenix, AZ |
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gic, VLSI CMOS circuits, VLSI layout, computer architecture, computer aided design tools. - Demonstrate experience with VLSI design relevant CAD tools such as Magic,... more |
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| Feb 07 | Graduate Intern (Austin) | Intel | Austin, TX |
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Some automatic place/route experiences using (Synopsys or equiv). We are also looking for some computer science students with knowledge in. 1. C/C /C#/Java, Perl, UNIX 2. Web... more |
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| Feb 07 | Sr. ASIC Design Eng (Timing) | Intel | Hillsboro, OR |
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and full-chip Static Timing Analysis using Synopsys Primetime or equivalent commercial tool, timing constraints generation and management, and timing convergence. - Demonstrate... more |
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| Feb 07 | Process Design Kit Engineer | Intel | Hillsboro, OR |
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standard CAD tool flows (e.g. Cadence, Synopsys) -- Establishing and executing a robust process design collateral test suite for PCK functionality/quality and release process --... more |
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| Feb 07 | Sr Process Design Kit Engineer | Intel | Hillsboro, OR |
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standard CAD tool flows (e.g. Cadence, Synopsys) -- Establishing and executing a robust process design collateral test suite for PCK functionality/quality and release process --... more |
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| Feb 07 | Hardware Developer 3 | Oracle | Broomfield, CO |
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contributor positionSystem Verilog based Synopsys VMM environment,analyzing functional and code coverage, debugging tests and thedesign. Additional activities include creating... more |
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| Feb 06 | ASIC & FPGA Design Eng Sr | Lockheed Martin | Sunnyvale, CA |
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Graphics Questa, Mentor Graphics AVM or Synopsys VMM or OVM or Specman eVC and eRM is ... environments, Mentor Graphics AVM or Synopsys VMM or OVM or Specman eVC and eRM is... more |
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| Feb 05 | Sr Sales Technical Leader | Cadence Design Systems | Irvine, CA |
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Formal Verification & DFT Solutions from Synopsys with Design Compiler or Cadence RTL Compiler and Physical Synthesis is required- Thorough Understanding of Static Timing and Low... more |
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| Feb 03 | Physical design/Place & Route (IC-Compiler and PrimeRail, UPF Flow) | S & D Engineering Solutions | Los Gatos, CA |
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will develop implementation flows using Synopsys design tools, including IC-Compiler ... Physical design engineer, Place & Route, Synopsys design tools, including IC-Compiler... more |
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| Feb 02 | Design Engineer-IEB-Hardware-Xbox (761335) Job | Microsoft | Mountain View, CA |
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of logic synthesis and timing analysis, Synopsys DC and Primetime experience desirable -Skilled in design verification, logic simulation, and formal verification -Experience with... more |
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| Feb 02 | Engineer | Samsung | Austin, TX |
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in low power design and experience using Synopsys Design Compiler Topographical (DCT); PrimeTime, Verilog, PERL, TCL, C/C++ programming languages and Unix Shell scripts. Employer... more |
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